As is known, flash memory devices comprise an array of cells arranged in rows and columns, wherein word lines connect the gate terminals of the cells arranged on a single row, and bit lines connect the drain terminals of the cells arranged on a single column. Individual memory array rows are thus addressed by a row decoder receiving an input coded address.
In flash memory devices, the memory array is divided into different sectors comprising cell blocks; in these devices the rows decoders permit reading and programming of individual cells of a sector, and only erasing of all the cells in the sector.
Such memory arrays are currently erased by applying a negative voltage to the gate terminals of the cells, for example, -10V, taking the source terminal to a positive voltage, for example, +5V, and leaving the drain terminal floating.
The method of erasing by sectors requires special measures when allocating the memory, since each time a datum stored in a sector is modified, it is necessary to erase and rewrite completely all the sector, and each sector has a separator device (which infer alia permits independent erasing from the other sectors) which has a large size (of approximately one hundred times the height of an array row). Consequently the design usually requires a compromise between the requirement to section the memory blocks as far as possible in order to erase only the components which need to, and not to increase excessively the total dimensions of the memory, owing to the presence of a large number of separators. However, this compromise does not always make it possible to obtain the best results.